PLL loop filter design for optimum integrated phase noise based on specified PLL parameters (Charge pump current, Icp, Divider N=Fout/Fref), VCO and Reference phase noise.

Look at the intersection of the open loop phase noise of your Reference (scaled by 20log(N), where N is Fout/Fref) and VCO open loop phase noise. The intersection of these two curves is f_{xsect}, and the corresponding angular frequency is ω_{xsect}=2πf_{xsect}.

Note the slope of the VCO open loop phase noise around the intersection (dB/decade). You can estimate it by looking at a decade offset in both directions, calculating the phase noise difference and dividing by 2.

Capacitance ratio, r=C1/C2 (as shown below), is typically bigger than or equal to 10. Integrated phase noise improves by about 10% when r is changed from 5 to 10, by additional 5% when going from r=10 to r=15, and by additional 2% going from r=15 to r=25. The choice of r depends on many things, such as: the required spurious suppression, settling time and filtering of the loop resistor noise.

**NOTE:** Loop resistor noise is assumed to be negligible. Reference phase noise is assumed to be flat around the intersection frequency, f_{xsect}.

Parameters used: r=C1/C2=10, VCOslope=29 dBc/Hz2, Kvco=200 MHz/V, Icp=5 mA, f_{xsect} =17 KHz, N=288, Ref PN= -80dBc/Hz at 14.4GHz (Fout). Which leads to the following loop filter values: R=39, C1=587nF, C2=58.7nF. (Note: C1/C2 are reversed in ADIsimPLL).

The following figure shows closed loop phase noise with the optimum loop filter working at 14.4GHz:

The table below shows the results of varying loop parameters to show that the calculator works as intended.

Values are integrated phase noise in degrees.

C1, C2 |
||||

-30% |
0 |
+30% |
||

R |
-30% |
2.38 | 2.37 | 2.38 |

0 |
2.32 | 2.31 | 2.32 | |

+30% |
2.32 | 2.32 | 2.32 |